Field of the Invention
The present invention relates to data processing. More particularly, this invention relates to the invalidation of stored address translations in address translation circuitry.
Description of the Prior Art
In a data processing apparatus which performs data processing operations with reference to data values stored in a memory, it is known to provide address translation circuitry which is configured to convert addresses of a first addressing system into addresses of a second addressing system. For example, this is the case where data processing circuitry (e.g. a CPU) of the data processing apparatus is configured to perform its data processing operations using virtual addresses, whilst the data values which are stored in a memory are referenced by the memory using physical addresses. Hence, in this example the address translation circuitry is configured to convert the virtual addresses into physical addresses. Given that some address translations may be repeatedly performed, it is further known to cache a set of address translations in storage provided in close association with the data processing circuitry to facilitate the performance of the address translation process and in particular to avoid the latency associated with retrieving address translation definitions from the memory. Such address translation circuitry is for example provided by a translation lookaside buffer (TLB).
Due to the fact that particular address translations are associated with particular sections of memory and therefore will typically have defined permissions associated with them such that the corresponding address translation can only be provided to a requester which is allowed to make the requested type of access to the specified memory address, it is further known that address translations can become invalid, for example after a context switch. A simple, yet blunt, technique for handling this situation is to flush all stored address translations that are locally stored (cached) in such situations so that any address translation that is requested thereafter must be determined with reference to a definitive reference source, such as a page table stored in memory, thus ensuring that the memory access permissions are correctly respected. However, this can result in rather inefficient usage of the local address translation storage (e.g. TLB) since the entire local storage content is deleted and therefore must be repopulated before the full benefit of having the local storage can be realised again.
It is also therefore known to configure such address translation circuitry to respond to an invalidation command which specifies a particular memory address and will cause any address translation circuitry in the data processing apparatus to invalidate a stored address translation corresponding to that address. Further, in order to allow the data processing circuitry to efficiently switch between contexts, or for example to host multiple virtual machines, it is also known to store an identifier (for example an address space identifier and/or a virtual machine identifier) in association with each locally stored address translation, such that any given address translation is only available to a requester which can provide a matching identifier. Accordingly, an invalidation command in such a data processing apparatus will also have a corresponding associated identifier, such that each process and/or virtual machine has control over the invalidation of its own stored address translations, but not over those of other processes/virtual machines.